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PowerQUICC III Course

This five-day course covers all hardware and software aspects of the PowerQUICC III device.


Course agenda:

  • MPC85xx Architecture

  • e500 Core Overview

  • Exception Processing

  • L1 and L2 Caches

  • Memory Management Unit (MMU)

  • Programmable Interrupt Controller

  • Reset and Boot Sequence

  • Memory Map and Local Bus Controller

  • DDR Controller

  • PCI/PCI-X Bus

  • Communication Processor Module (CPM) Overview

  • DMA Controller

  • Three Speed Ethernet Controller

  • RapidIO Interface


 

 

 

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